In the display technology field, the flat panel display device has been gradually replaced the Cathode Ray Tube (CRT) display. The flat panel device possesses advantages of high image quality, power saving, thin body and no irradiation. Thus, it has been widely applied in various consumer electrical products, such as mobile phones, televisions, personal digital assistants, digital cameras, notebooks, and laptops, and becomes the major display device.
The common flat panel display device at present mainly comprises a Liquid Crystal Display (LCD) and an Active Matrix Organic Light-Emitting Diode (AMOLED). The Thin Film transistors (TFT) can be formed on a glass substrate or a plastic substrate. Generally, the thin film transistors are employed as switching elements and driving elements utilized in the flat panel display devices such as LCDs, AMOLEDs.
The oxide semiconductor TFT technology is the most popular skill at present. The oxide semiconductor has higher electron mobility. The manufacturing process of the oxide semiconductor is simple in comparison with the Low Temperature Poly-silicon semiconductor and has higher compatibility with the amorphous silicon process. It can be applied to display devices such as LCDs, AMOLEDs and has the great opportunity of application development. However, the traditional oxide semiconductor TFT is the single gate structure in general. The stability issues including the environment stability, the stress bias stability and mask stability issues exist. For solving the stability issues of the single gate oxide semiconductor TFT, a dual gate structure TFT substrate is proposed for promoting the stability of the TFT and reducing the drift of the threshold voltage (Vth). As shown in FIG. 1, a dual gate TFT substrate according to prior art comprises: a substrate 10, a bottom gate 20, a first isolation layer 30, an oxide island shaped semiconductor layer 40, a second isolation layer 50, a source/a drain 60, a third isolation layer 70, a top gate 80, a fourth isolation layer 90 and a pixel electrode 100 sequentially stacked on the substrate 10. The source/the drain 60 contact the oxide island shaped semiconductor layer 40 with via holes penetrating the second isolation layer 50 to form electrical connections; the pixel electrode 100 contacts the source/the drain 60 with via holes penetrating the fourth isolation layer 90 and the third isolation layer 70 to form electrical connections.
Particularly, in the dual gate TFT substrate according to prior art, the bottom gate 20 is positioned on the substrate 10, and the source/the drain 60 are positioned on the second isolation layer 50, and the top gate 80 is positioned on the third isolation layer 70. The source/the drain 60 and the top gate 80 are respectively at different layers. Therefore, one single mask is required for manufacturing one of the bottom gate 20, the source/the drain 60 and the top gate 80. The necessary amount of the masks is more and the process flow is longer. The manufacturing process is more complicated and the production cost is higher.